1. Field of the Invention
The present invention relates to an electrostatic discharge protection device used in a semiconductor integrated circuit for protecting the semiconductor integrated circuit from breaking due to an electrostatic charge flowing into or out of the circuit (electrostatic discharge phenomenon). The present invention also relates to a method for producing such an electrostatic discharge protection device, and an electrostatic discharge protection circuit using the same.
2. Description of the Related Art
The electrostatic discharge, as discussed in the field of semiconductor integrated circuits, is a phenomenon in which an electrostatic charge flows into a semiconductor integrated circuit from an electrostatically charged person or machine, or an electrostatic charge flows into an external conductor from a semiconductor integrated circuit which has been electrostatically charged by friction, etc. When the electrostatic discharge phenomenon occurs, an amount of electrostatic charge flows into or out of a semiconductor integrated circuit in a moment. Thus, an excessive current flows through the semiconductor integrated circuit device, whereby an excessive voltage flows through an internal circuit. Consequently, junction breakdown, line melting, oxide film dielectric breakdown, or the like, may occur, thereby breaking the semiconductor integrated circuit.
In order to prevent the semiconductor integrated circuit from breaking due to the electrostatic discharge phenomenon, an electrostatic discharge protection device is commonly provided between an external terminal and an internal circuit of a semiconductor integrated circuit so as to form a bypass circuit for static electricity. Such an electrostatic discharge protection device is provided during a step in the production of the semiconductor integrated circuit. In order not to increase the production cost of a semiconductor integrated circuit, it is desirable to provide the electrostatic discharge protection device without performing any additional step.
Commonly-employed electrostatic discharge protection devices include current limiting elements for limiting a transient current flowing in a semiconductor integrated circuit, such as a diffused resistor, and a polysilicon resistor. Other such protection circuits include a voltage clamping element for suppressing the voltage applied to an internal circuit, such as a diode, a thyristor, a MOS transistor, and a bipolar transistor.
A thyristor, as a current clamping element, can advantageously produce an excessive discharge current. However, a trigger voltage at which the thyristor is turned ON is generally high, e.g., about 25 V to about 40 V, whereby the semiconductor integrated circuit may break before the thyristor is activated. In view of this, thyristors have been adjusted to reduce the trigger voltage.
FIG. 24 is a cross-sectional view illustrating an exemplary conventional electrostatic discharge protection device, and more particularly, a thyristor that can be triggered by a low voltage (Japanese Patent No. 2505652).
Referring to FIG. 24, an n-type well 2 is provided in a p-type substrate 1 as an n-type impurity diffused layer. A p-type anode high impurity concentration region 4 and an n-type anode gate high impurity concentration region 5 are provided in the n-type well 2. A p-type high impurity concentration region 55 is provided across the boundary between the n-type well 2 and the p-type substrate 1, so that a portion of the p-type high impurity concentration region 55 is surrounded by the n-type well 2 and another portion thereof is surrounded by the p-type substrate 1. An n-type cathode high impurity concentration region 6 and a p-type cathode gate high impurity concentration region 7 are provided in another region of the p-type substrate 1 away from the n-type well 2. The p-type anode high impurity concentration region 4 and the n-type anode gate high impurity concentration region 5 are connected to an anode terminal 36 via a contact 16 and a metal 18. The n-type cathode high impurity concentration region 6 and the p-type cathode gate high impurity concentration region 7 are connected to a cathode terminal 54 via another contact 16 and another metal 53.
Referring to FIG. 25, the low voltage thyristor as illustrated in FIG. 24 maybe provided between a power supply line 52 and a reference voltage line 45 of a semiconductor integrated circuit. An anode terminal 36 of the electrostatic discharge protection device 56 is connected to the power supply line 52, and the cathode terminal 54 of the electrostatic discharge protection device 56 is connected to the reference voltage line 45. An excessive voltage due to an electrostatic discharge is applied to the power supply line 52. When the electrostatic discharge reaches the trigger voltage of the thyristor provided in the electrostatic discharge protection device 56, the thyristor is turned ON, thereby forming a low-resistance path between the power supply line 52 and the reference voltage line 45. The low-resistance path bypasses an electrostatic charge flowing into the device from a power supply terminal 51 to a reference voltage terminal 44, thereby preventing breakdown of a semiconductor integrated circuit 57 connected to the power supply line 52 and the reference voltage line 45.
Where the p-type high impurity concentration region 55 is not provided, the trigger voltage of the thyristor is determined by the breakdown voltage between the p-type substrate 1 and the n-type well 2. With the production process of a common CMOS semiconductor integrated circuit, the trigger voltage will be as high as about 25 V to about 40 V. With such a high voltage, internal circuits of the semiconductor integrated circuit 57 will break before the thyristor is turned ON. The trigger voltage of the thyristor illustrated in FIG. 24 is determined by the breakdown voltage between the p-type high impurity concentration region 55 and the n-type well 2. Due to the presence of the p-type high impurity concentration region 55, the breakdown voltage can be reduced below the breakdown voltage between the p-type substrate 1 and the n-type well 2.
Since the minimum process dimension of a semiconductor integrated circuit became minute, and a demand for a faster operation of an integrated circuit increased, a salicide (self-alignment silicide) step has been employed in order to reduce the source/drain diffused resistance or the gate line resistance of a MOS transistor. In the salicide step, a silicon substrate surface and a polysilicon surface, whose resistances are to be reduced, are first adjusted to be exposed, on which a high melting point metal such as titanium or cobalt is deposited. Then, a heat treatment is performed so as to provide an alloy (silicide) of silicon and the high melting point metal.
In the salicide step in the CMOS process, a silicide layer is provided on a portion of a silicon surface which is not covered with a gate oxide film or a device separation insulator of the MOS transistor. In the thyristor of FIG. 24, which can be triggered by a low voltage, the silicon surfaces of the p-type high impurity concentration region 55 (to be the trigger) and the n-type well 2 are both covered with the silicide layer. Then, the p-type high impurity concentration region 55 and the n-type well 2 are shortcircuitted with each other, whereby breakdown can no longer occur therebetween. Due to the shortcircuit, the n-type anode gate high impurity concentration region 5, the n-type well 2, the p-type high impurity concentration region 55, the p-type substrate 1, and the p-type cathode gate high impurity concentration region 7 are shortcircuitted with one another, whereby the anode terminal 36 and the cathode terminal 54 are shortcircuitted with each other.
A way of avoiding the shortcircuit between the p-type high impurity concentration region 55 and the n-type well 2 is to provide a silicidation inhibiting insulator on the silicon surface of the pn junction between the p-type high impurity concentration region 55 and the n-type well 2, in a step separate from the step of forming a semiconductor integrated circuit and prior to the salicide step. This method, however, adds a further step or photomask to the semiconductor integrated circuit process, thereby increasing the production cost of the semiconductor integrated circuit.
According to one aspect of this invention, an electrostatic discharge protection device is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.
In one embodiment of the invention, the insulator section includes: a gate oxide film formed between the n-type cathode high impurity concentration region and the p-type anode high impurity concentration region for providing a gate of a MOS transistor of the semiconductor integrated circuit; a polysilicon patterned on the gate oxide film; and a gate sidewall insulator provided on a sidewall of the gate oxide film and a sidewall of the polysilicon for electrically insulating the silicide layer formed on the surface of the n-type cathode high impurity concentration region from the silicide layer formed on the surface of the p-type anode high impurity concentration region.
In one embodiment of the invention, the electrostatic discharge protection device is formed in a p-type semiconductor substrate. The n-type cathode high impurity concentration region is formed in an n-type well. A portion of the p-type anode high impurity concentration region is included in the n-type well. Another portion of the p-type anode high impurity concentration region is included in the p-type semiconductor substrate or a p-type well.
In one embodiment of the invention, the electrostatic discharge protection device is formed in a p-type semiconductor substrate. The p-type anode high impurity concentration region is formed in the p-type semiconductor substrate or a p-type well. A portion of the n-type cathode high impurity concentration region is included in an n-type well. Another portion of the n-type cathode high impurity concentration region is included in the p-type semiconductor substrate or the p-type well.
In one embodiment of the invention, the electrostatic discharge protection device is formed in an n-type semiconductor substrate. The n-type cathode high impurity concentration region is formed in the n-type semiconductor substrate. A portion of the p-type anode high impurity concentration region is included in a p-type well. Another portion of the p-type anode high impurity concentration region is included in the n-type semiconductor substrate or an n-type well.
In one embodiment of the invention, the electrostatic discharge protection device is formed in an n-type semiconductor substrate. The p-type anode high impurity concentration region is formed in a p-type well. A portion of the n-type cathode high impurity concentration region is included in the p-type well. Another portion of the n-type cathode high impurity concentration region is included in the n-type semiconductor substrate or an n-type well.
In one embodiment of the invention, the insulator section includes a device separation insulator which is formed between the n-type cathode high impurity concentration region and the p-type anode high impurity concentration region for providing a device separation region of a MOS transistor of the semiconductor integrated circuit.
In one embodiment of the invention, the electrostatic discharge protection device is formed in a p-type semiconductor substrate. The n-type cathode high impurity concentration region is formed in an n-type well. A portion of the p-type anode high impurity concentration region is included in the n-type well. Another portion of the p-type anode high impurity concentration region is included in the p-type semiconductor substrate or a p-type well.
In one embodiment of the invention, the electrostatic discharge protection device is formed in a p-type semiconductor substrate. The p-type anode high impurity concentration region is formed in the p-type semiconductor substrate or a p-type well. A portion of the n-type cathode high impurity concentration region is included in an n-type well. Another portion of the n-type cathode high impurity concentration region is included in the p-type semiconductor substrate or the p-type well.
In one embodiment of the invention, the electrostatic discharge protection device is formed in an n-type semiconductor substrate. The n-type cathode high impurity concentration region is formed in the n-type semiconductor substrate. A portion of the p-type anode high impurity concentration region is included in a p-type well. Another portion of the p-type anode high impurity concentration region is included in the n-type semiconductor substrate or an n-type well.
In one embodiment of the invention, the electrostatic discharge protection device is formed in an n-type semiconductor substrate. The p-type anode high impurity concentration region is formed in a p-type well. A portion of the n-type cathode high impurity concentration region is included in the p-type well. Another portion of the n-type cathode high impurity concentration region is included in the n-type semiconductor substrate or an n-type well.
According to another aspect of this invention, a method for producing an electrostatic discharge protection device of the present invention is provided. The method includes the steps of: forming an n-type cathode high impurity concentration region; forming a p-type anode high impurity concentration region; and forming an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.
In one embodiment of the invention, the step of forming the insulator section includes the steps of: forming, on a silicon substrate, a gate oxide film to be a gate of a MOS transistor of a semiconductor integrated circuit; patterning, on the gate oxide film, a polysilicon to be a gate electrode of the MOS transistor; implanting ions of a p-type impurity using the polysilicon and a p-type ion implantation resist as masks; implanting ions of an n-type impurity using the polysilicon and an n-type ion implantation resist as masks; forming a gate sidewall insulator on a sidewall of the polysilicon and a sidewall of the gate oxide film; and forming a silicide layer on a surface of the n-type cathode high impurity concentration region and a surface of the p-type anode high impurity concentration region.
In one embodiment of the invention, the method further includes, before the step of implanting ions of a p-type or n-type impurity, the step of: where the n-type cathode high impurity concentration region of the trigger diode of the thyristor forms a PN junction with a p-type substrate or a p-type well, arranging an edge of a p-type ion implantation photomask at a position in the polysilicon region which is shifted away from an edge of an n-type impurity implantation region.
In one embodiment of the invention, the method further includes, before the step of implanting ions of a p-type or n-type impurity, the step of: where the p-type cathode high impurity concentration region of the trigger diode of the thyristor forms a PN junction with an n-type substrate or an n-type well, arranging an edge of an n-type ion implantation photomask at a position in the polysilicon region which is shifted away from an edge of a p-type impurity implantation region.
In one embodiment of the invention, the step of forming the insulator section includes the steps of: forming a device separation insulator for separating an active region, in which a MOS transistor of the semiconductor integrated circuit is formed, from another such active region; implanting ions of a p-type impurity using the device separation insulator and a p-type ion implantation resist as masks; implanting ions of an n-type impurity using the device separation insulator and an n-type ion implantation resist as masks; and forming a silicide layer on a surface of the p-type anode high impurity concentration region and a surface of the n-type cathode high impurity concentration region.
In one embodiment of the invention, the method further includes, before the step of implanting ions of a p-type or n-type impurity, the step of: where the n-type cathode high impurity concentration region of the trigger diode of the thyristor forms a PN junction with a p-type substrate or a p-type well, arranging an edge of a p-type ion implantation photomask at a position on the device separation insulator at or near the center of the trigger diode which is shifted away from an edge of an n-type impurity implantation region.
In one embodiment of the invention, the method further includes, before the step of implanting ions of a p-type or n-type impurity, the step of: where the p-type anode high impurity concentration region of the trigger diode of the thyristor forms a PN junction with an n-type substrate or an n-type well, arranging an edge of an n-type ion implantation photomask at a position on the device separation insulator at or near the center of the trigger diode which is shifted away from an edge of a p-type impurity implantation region.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through an input/output terminal thereof to a reference voltage line is provided. The electrostatic discharge protection circuit includes: the electrostatic discharge protection device having the trigger diode according to the present invention; and a protection diode. The electrostatic discharge protection device and the protection diode are arranged in parallel between an input/output signal line and the reference voltage line of the semiconductor integrated circuit. An anode and an anode gate of a thyristor provided in the electrostatic discharge protection device and a cathode of the protection diode are connected to the input/output signal line. A cathode and a cathode gate of the thyristor and an anode of the protection diode are connected to the reference voltage line. The electrostatic discharge protection device further includes a resistor, the resistor being formed in a well, which has a conductivity type opposite to that of a substrate, between the anode of the thyristor and the cathode of the protection diode.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through an input/output terminal thereof to a power supply line is provided. The electrostatic discharge protection circuit includes: the electrostatic discharge protection device having the trigger diode according to the present invention; and a protection diode formed in an n-type substrate or an n-type well. The electrostatic discharge protection device and the protection diode are arranged in parallel between an input/output signal line and a power supply line of the semiconductor integrated circuit. An anode and an anode gate of a thyristor provided in the electrostatic discharge protection device and a cathode of the protection diode are connected to the power supply line of the semiconductor integrated circuit. A cathode of the thyristor and an anode of the protection diode are connected to the input/output signal line. A cathode gate of the thyristor is connected to the reference voltage line. The electrostatic discharge protection device further includes a resistor, the resistor being formed in a well, which has a conductivity type opposite to that of a substrate, between the cathode of the thyristor and the anode of the protection diode.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through a power supply line thereof to a reference voltage line is provided. The electrostatic discharge protection circuit includes: the electrostatic discharge protection device having the trigger diode according to the present invention. The electrostatic discharge protection device is arranged between the power supply line and the reference voltage line of the semiconductor integrated circuit. An anode and an anode gate of a thyristor provided in the electrostatic discharge protection device are connected to the power supply line. A cathode and a cathode gate of the thyristor are connected to the reference voltage line.
In one embodiment of the invention, the n-type cathode high impurity concentration region and the p-type anode high impurity concentration region of the protection diode are produced according to the method of producing an electrostatic discharge protection device of the present invention.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through any of an input/output terminal, a reference voltage terminal, and a power supply line thereof, to another of the input/output terminal, the reference voltage terminal, and the power supply terminal, is provided. The electrostatic discharge protection circuit includes: a first electrostatic discharge protection circuit according to the present invention; a second electrostatic discharge protection circuit according to the present invention; and a third electrostatic discharge protection circuit according to the present invention. The first electrostatic discharge protection circuit is provided between an input/output signal line and a reference voltage line of the semiconductor integrated circuit. The second electrostatic discharge protection circuit is provided between the input/output signal line and a power supply line of the semiconductor integrated circuit. The third electrostatic discharge protection circuit is provided between the power supply line and the reference voltage line.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through any of an input/output terminal, a reference voltage terminal, and a power supply line thereof, to another of the input/output terminal, the reference voltage terminal, and the power supply terminal, is provided. The electrostatic discharge protection circuit includes first, second and third electrostatic discharge protection devices each having a trigger diode according to the present invention. An anode and an anode gate of a first thyristor provided in the first electrostatic discharge protection device are connected to a power supply line of the semiconductor integrated circuit. A cathode of the first thyristor is connected to an input/output signal line of the semiconductor integrated circuit. A cathode gate of the first thyristor is connected to a reference voltage line of the semiconductor integrated circuit. An anode and an anode gate of a second thyristor provided in the second electrostatic discharge protection device are connected to the input/output signal line of the semiconductor integrated circuit. A cathode and a cathode gate of the second thyristor are connected to the reference voltage line of the semiconductor integrated circuit. An anode and an anode gate of a third thyristor provided in the third electrostatic discharge protection device are connected to the power supply line of the semiconductor integrated circuit. A cathode and a cathode gate of the third thyristor are connected to the reference voltage line of the semiconductor integrated circuit.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through any of an input/output terminal, a reference voltage terminal, and a power supply line thereof, to another of the input/output terminal, the reference voltage terminal, and the power supply terminal, is provided. The electrostatic discharge protection circuit includes: a first electrostatic discharge protection circuit according to the present invention; and a second electrostatic discharge protection circuit according to the present invention. The first electrostatic discharge protection circuit is provided between an input/output signal line and a reference voltage line of the semiconductor integrated circuit. The second electrostatic discharge protection circuit is provided between a power supply line and the reference voltage line of the semiconductor integrated circuit.
According to still another aspect of this invention, an electrostatic discharge protection circuit for bypassing an electrostatic surge entering a semiconductor integrated circuit through any of an input/output terminal, a reference voltage terminal, and a power supply line thereof, to another of the input/output terminal, the reference voltage terminal, and the power supply terminal, is provided. The electrostatic discharge protection circuit includes: a first electrostatic discharge protection device having a trigger diode according to the present invention between a reference voltage line and an input/output signal line of the semiconductor integrated circuit; and a second electrostatic discharge protection device having a trigger diode according to the present invention between the reference voltage line and a power supply line of the semiconductor integrated circuit. An anode and an anode gate of a first thyristor provided in the first electrostatic discharge protection device are connected to an input/output signal line of the semiconductor integrated circuit. A cathode and a cathode gate of the first thyristor are connected to the reference voltage line of the semiconductor integrated circuit. An anode and an anode gate of a second thyristor provided in the second electrostatic discharge protection device are connected to the power supply line of the semiconductor integrated circuit. A cathode and a cathode gate of the second thyristor are connected to the reference voltage line of the semiconductor integrated circuit.
Thus, the invention described herein makes possible the advantages of (1) providing an electrostatic discharge protection device which can be provided without adding any special step or photomask to the semiconductor integrated circuit production process even when a salicide step is employed in the semiconductor integrated circuit production: (2) providing a method for producing the same; and (3) providing an electrostatic discharge protection circuit using the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.